Explore how networking has become the primary constraint for AI. Vic Shaker discusses data center infrastructure, GPU scaling, and solving the compute bottleneck.

We are living in an era where the biggest computers in the world no longer fit in a single box—they occupy entire buildings. We’ve moved from the era where we cared about 'per core' performance to an era where we need 100,000 GPUs to act like one.
Create a 15-20 minute audio lesson strictly based on the provided podcast transcript about AI networking and hardware. Focus on why data movement between chips (Scale Up, Scale Out, Scale Across) is the current bottleneck, the trade-offs between copper and optical connections, and the emerging role of Co-Packaged Optics. Follow the user's detailed 11-point structure, maintaining a conversational professor-like tone for a non-technical audience. Adhere strictly to the transcript for all technical details and claims, tagging them with confidence levels as requested. VERBATIM SOURCE: "The biggest computers in the world today are basically no…"



The AI networking bottleneck refers to the growing gap between chip speed and the wires connecting them. While individual processors have become incredibly fast, the networking infrastructure hasn't kept pace. Vic Shaker explains that even the most powerful processors waste potential if they are forced to wait for data to travel across a room from another chip, making networking the primary constraint on modern AI development.
Modern data center infrastructure has shifted from individual computers to massive, distributed systems that occupy entire buildings. Because massive AI models cannot fit on a single laptop or box, thousands of chips must now function as a single, distributed brain. This shift requires a total rethink of how machines are built, moving the focus from per-core performance to the seamless integration of 100,000 GPUs acting as one unit.
GPU scaling is now limited by networking because compute capability has grown much faster than the ability to hook chips together. Vic Shaker points out that the bottleneck is no longer the silicon itself, but the interconnects between them. To achieve the scale needed for AI, the industry must solve how data moves between chips, whether through copper or optics, to ensure that distributed computing power isn't wasted.
Criado por ex-alunos da Universidade de Columbia em San Francisco
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Criado por ex-alunos da Universidade de Columbia em San Francisco
